1. Technical Field of the Invention
This invention relates to digital signal processing and, more particularly, to an all digital phase-locked loop (ADPLL) circuit and method of recovering a bit clock signal from a sampled waveform.
2. Description of Related Art
Compact disc (CD) players suffer from several sources of signal degradation. For example, high-frequency phase fluctuations may be caused by jitter due to disc asymmetry. Low-frequency phase variation may be caused by wander due to player and/or disc eccentricity. In addition, disc imperfections such as xe2x80x9cblack dotxe2x80x9d cause loss-of-signal indications, and scratches on the disc cause persistent loss-of-frame indications. Also, excessive asymmetry may disturb the frame synchronization by causing, for example, an 11T/11T frame synchronization sequence to appear as a 10T/12T or 12T/10T sequence.
The high frequency (HF) signal from the CD xe2x80x9cpickupxe2x80x9d is digitized, equalized (via digital filtering), and the direct current (DC) component is eliminated through a slicing operation to form a sampled waveform. If the slicing threshold is not correct, errors in measured run lengths (pulse lengths in the input data waveform) and phase errors can result. Finally, errors in angular velocity may cause signal distortion.
FIG. 1 is an illustration of a typical analog HF signal 11 from a CD pickup shown on the same time scale with a standard sawtooth waveform of a clock signal. The CD pickup converts the reflected light from the surface of the CD to the analog HF signal. A slicing threshold 12 for elimination of the DC component is also indicated; the intersections of the waveform and the slicing threshold mark waveform transitions 13 and 14. The data that is taken off the CD is encoded in the length of the pulses in the analog HF signal 11. Therefore, it is very important to measure the pulse lengths (run lengths) correctly.
FIG. 1 illustrates one waveform pulse having a run length of 4T, where T is the period of an embedded clock signal. An illustration of a standard sawtooth waveform 15 of an embedded clock (oscillator) signal is provided below the analog HF signal using the same time scale. The clock signal is generated by a conventional digital oscillator with a range from zero (0) to 2xcfx80 radians. Normally, samples are taken much more frequently than shown; however, the principles illustrated are the same.
Utilizing conventional techniques to measure run length, a counter simply measures the number of clock pulses during a waveform pulse. The clock utilizes a 2xcfx80 accumulator. Every time the accumulator overflows, a discontinuity (vertical clock edge) 16 occurs. The clock edges 16 are then counted between transitions 13 and 14 (i.e., between intersections of the waveform and the slicing threshold) in the incoming data waveform (HF signal) 11 in order to measure the run length. This is effectively counting multiples of 2xcfx80 in phase. Every time the oscillator goes through 2xcfx80 phase, equates to one bit period.
Superimposed on the sawtooth clock waveform of FIG. 1 is a stem diagram illustrating the digitized and sampled data points 17 extracted from the analog HF signal 11. The data points must be joined together to obtain a digitized waveform. However, as can be seen from FIG. 1, there is no way of identifying the transitions; and therefore, no way of knowing if an accumulator is running at the correct rate or how many clock periods are present between transitions. Therefore, the run length is not measurable.
Traditionally, when using digital signal processing (DSP) techniques for clock recovery, the sampling rate is very fast. The oscillator which produces the clock waveform 15 includes an accumulator that accumulates the phase increment produced during each analog-to-digital conversion (ADC) sample period (approximately 16 MHZ). For low bit rates (for example, 1xc3x97CD spin speed producing a maximum bit rate of approximately 4 MHZ), this update rate is sufficient for run length detection. However, for higher bit rates (for example, 4xc3x97CD spin speed producing bit rates of approximately 16 MHZ, the update rate is approximately equal to the ADC sample rate and is, therefore, too coarse for run length detection. It is not economically practical (or even possible) to sample quickly enough to accurately measure the run length utilizing conventional methods.
There are no known prior art teachings of a solution to the aforementioned deficiencies and shortcomings such as that disclosed herein.
In order to overcome the disadvantages of existing CD players, it would be advantageous to have an HF synchronization circuit and method for correcting the above problems. In particular, it would be advantageous to have a method of accurately measuring run lengths while utilizing a low sampling rate. The present invention provides such a circuit and method.
In one aspect, the present invention is a method of accurately measuring a pulse run length in a high frequency (HF) data signal while utilizing a low analog-to-digital conversion (ADC) sampling rate. The method includes the steps of generating a sawtooth clock waveform, ranging in phase from zero (0) to 32xcfx80 radians, with an oscillator having an accumulator register. This is followed by detecting a first zero-crossing transition of the HF data signal at the leading edge of the pulse run length and measuring a first phase increment when the first zero-crossing transition is detected. The method then initializes the most significant bits (MSBs) of the accumulator register to adjust the measured first phase increment so that it lies in a range between zero (0) and 2xcfx80 radians and then accumulates phase increments until a second zero-crossing transition of the HF data signal is detected at the trailing edge of the pulse run length. This is followed by measuring a second phase increment when the second zero-crossing transition is detected, calculating an accumulated phase difference by subtracting the first phase increment from the measured second phase increment, and dividing the accumulated phase difference by 2xcfx80 to obtain the pulse run length.
In another aspect, the present invention is a method of recovering an embedded bit clock in successive transitions of a digitized high frequency signal. The method comprises the steps of generating a sawtooth waveform having a phase from 0 to a predetermined multiple of 2xcfx80 radians. The phase of the sawtooth waveform is initialized in a range of between 0 and 2xcfx80 radians beginning at a first transition of the high frequency signal. At a second transition of the high frequency signal, an end of the sawtooth waveform is determined. The number of 2xcfx80 radians in the generated sawtooth waveform between the first and second transitions of the high frequency signal is counted. The bit clock in successive transitions of the digitized high frequency signal is recovered by dividing the number of 2xcfx80 radians counted between the first and second transitions by 2xcfx80.
In another aspect, the present invention is a system for accurately measuring a pulse run length in a high frequency (HF) data signal while utilizing a low analog-to-digital conversion (ADC) sampling rate. The system includes an oscillator which generates a sawtooth clock waveform ranging in phase from zero (0) to 32xcfx80 radians and accumulates phase increments in its accumulator register. The system also includes an interpolator which detects a first zero-crossing transition of the HF data signal at the leading edge of the pulse run length and which detects a second zero-crossing transition of the HF data signal at the trailing edge of the pulse run length. A phase detector measures a first phase increment when the interpolator detects the first zero-crossing transition and measures a second phase increment when the second zero-crossing transition is detected. The system also includes means for initializing the MSBs of the accumulator register to adjust the measured first phase increment so that it lies in a range between zero (0) and 2xcfx80 radians, means for calculating an accumulated phase difference by subtracting the first phase increment from the measured second phase increment, and means for dividing the accumulated phase difference by 2xcfx80 to obtain the pulse run length.
In another aspect, the present invention is to a system for accurately measuring a pulse width in a high frequency signal that utilizes a low sampling rate. The system comprises an oscillator generating a sawtooth clock waveform that ranges in phase from zero (0) to a multiple of 2xcfx80 radians. The oscillator has an accumulator register that accumulates phase increments. An interpolator detects a first transition of the signal at a leading edge of the pulse and a second transition of the signal at a trailing edge of the pulse. A phase detector measures the oscillator phase when the interpolator detects the first transition and a second phase increment when the interpolator detects the second transition. Apparatus initiating the accumulator register most significant bits (MSBs) adjusts the measured first phase increment to lie in a range between zero (0) and 2xcfx80 radians. Apparatus for calculating an accumulated phase difference subtracts the initialized first phase increment from the measured second phase increment and divides the accumulated phase difference by 2xcfx80 to obtain the pulse width.
In another aspect, the present invention is to a high frequency control circuit. The circuit comprises an analog to digital converter to convert a high frequency analog signal into a high frequency digitized signal. An equalizer boosts the amplitude of narrower pulses while introducing minimal additional inter-symbol interference of the high frequency digitized signal into a high frequency digitized, equalized signal. A high-pass filter slices a direct current component from the digitized, equalized signal into a digitized, equalized and sliced high frequency signal. A high frequency synchronization control loop includes an all digital locked loop for recovering a bit clock embedded in a digitized high frequency signal. The control loop has a phase detector providing a digital output in response to a transition of the digitized high frequency signal. A low pass filter provides an output frequency signal in response to the digital output signal from the phase detector. A variable oscillator provides a sawtooth waveform signal ranging in phase from 0 to a predetermined multiple of 2xcfx80 radians to the phase detector in response to the output frequency from the low pass filter. A radians number signal representing an accumulation of the number of radians is provided to the phase detector at the first transition of the high frequency signal and at the second transition of the high frequency signal. A measuring device provides a frequency, phase signal in response to the accumulated radians number signal and a preselected constant of 2xcfx80 radians.